VirtusLang Workbench — Virtus Cyber Academy

Source (.virtus / .S)

VM bytecode (.vm)

(empty)

Assembly (.S)

(empty)

Object file (.vof, hex view)

(empty)

Loader hex (.hex)

(empty)

Compile log

Program (.hex)

(empty — pick an example or upload .hex)

CPU state

(emulator not started)

Memory (data segment)

base

(no data)

Emulator log

Verilog source (.v)

Yosys log (.json netlist)

(not started)

Gate-level netlist (synthesized cells)

Run synthesis to see your gate-level netlist.

These are the actual gates your HDL produced. Each box is a synthesized cell; each line is a wire. The Tang Nano 20K (GW2A-18) has 20,736 LUT4 cells available and the Tang Primer 25K (GW5A-25) has 23,040 — your design used (synth first). See the silicon-level reading guide for what these look like in real fabricated NMOS (Z80, MOS 6502, Intel 4004).

Operate your design (in-browser simulator)

tick: 0

Synthesize a design to operate it here. The canonical 5-bit counter (matching the tn20k_blink pattern) loads automatically after the first successful synth so you can step the clock and watch the counter advance.

This is your design running. Same gates, same wires, same clock. The simulator steps through cycles identical to what the silicon would do. When you are ready to flash to a real Tang Primer 25K, the next step is bitstream generation, a small server hop. For everything you can verify here in simulation, the hardware will do exactly the same thing. See the silicon-level reading guide and the gate-level netlist pane above for the structural view.

Place & Route log (nextpnr)

(not started)

Bitstream pack (gowin_pack)

(not started)

Flash to FPGA

Or run this command locally after downloading .fs:

openFPGALoader --board tangnano20k --write-flash bitstream.fs

Tang Primer 25K (GW5A-25) uses the same flash command with a different board flag: openFPGALoader --board tangprimer25k --write-flash bitstream.fs

Pipeline log

Browser capability report (runtime probes)

(probing on page load — click "Run capability self-test" to refresh)

Source (.S)

RV32I-Lite assembly

Register file (x0–x7)

read writeback

Disassembly + PC

PC = 0x00000000

Memory window

(no program loaded)

ALU panel

(idle)

Trace log

This is the fetch-decode-execute cycle as a physical act. Each Step click advances the PC by one instruction: the byte at M[PC] is decoded into opcode + register fields, the source registers (highlighted amber) are read into the ALU, the ALU produces a value, and the destination register (highlighted green) takes the result. Branch and load/store instructions add a PC-redirect or a memory access. After 21 steps the canonical sum_to_n.S program halts with x3 = 15 and M[0x104] = 15 for N = 5, matching the Lab 5.2 worksheet's hand-trace contract. See the encoding card for the bit-field layout that drives the decoder.