VCA-CSA-101: Fundamentals of Computing Systems

Classroom

Full course content (weekly modules, labs, capstone packet, instructor guide) lives in the Virtus Cyber Academy classroom, which is in active build. The public preview is on the way.

Open in classroom

Course Overview

Graduates can trace a Python statement through the compiler, through the bytecode, through the CPU instructions, through the logic gates, through the transistors. Not as a memorized mantra, but as a model they have personally built. This is not reverse engineering. It is the converse: forward engineering of a complete computing stack. But it is the ideal conceptual foundation for reverse engineering, because a student who has built each layer of the stack can reason about each layer as a target.

Principal reading: Nisan & Schocken, The Elements of Computing Systems: Building a Modern Computer from First Principles, 2nd ed. (MIT Press, 2021). Tools are Virtus-original - a Virtus-built HDL simulator, assembler, VM interpreter, and compiler test harness, functionally equivalent to what students need to complete the textbook's projects.

Position relative to peer offerings. CSA-101 sits between (a) university-level computer-architecture survey courses (Patterson & Hennessy Computer Organization & Design; Tanenbaum Structured Computer Organization) which present an architecture as something to read about, and (b) the From-Nand-to-Tetris path which builds a software stack on a 16-bit toy machine but stops short of physical silicon and an open-source FPGA toolchain. CSA-101 is the first course in the curriculum that builds an industry-sane RISC-V variant (RV32I-Lite), places it on a Tang Primer 25K FPGA the student keeps (canonical Phase-1 hardware; Tang Nano 20K supported as advanced-track alternative), and weaves Petzold's CODE through chapter prose as substantive narrative rather than as supplementary recommended reading. The Virtus Co-Processor (VCP) extension carries the curriculum thread forward into VCA-RE-101's SB6141 lab target and the future Virtus Console capstone build.

How the course teaches. Three habits run through every chapter. First, you'll read short passages from Charles Petzold's CODE alongside the chapter material, about thirty-seven such readings across the course, each tied to specific pages so the physical-intuition spine stays connected to the formal machinery. Second, you'll keep a personal tool journal - a Markdown file in your course Git repo with one paragraph per new tool you meet (CSA-101 introduces about twenty-three of them, from the HDL simulator through QEMU). Third, every chapter compares the design choices Virtus makes against the industry equivalents (full RV32I, x86_64, ARMv8, MIPS, the 6502 as a historical anchor) so you finish knowing not just what Virtus does but why and how that matches or differs from the systems you'll meet outside class. A specific thread, the SB6141 cable modem you'll later reverse-engineer in VCA-RE-101. Runs through chapters 4, 5, and 6a as a forward pointer.

The workbench

Every CSA-101 toolchain stage runs in your browser. The academy workbench (all three tabs LIVE) delivers the full pipeline as a three-tab single page; no local installs, no toolchain version drift, no "but it works on my laptop" debugging tax. The same workbench also unlocks the browser-only path for students taking the course before their hardware kit arrives or in regions where shipping is impractical - the same Virtus OS lessons running entirely in your browser. The silicon bring-up in Module 5 is the single graded checkpoint that requires hardware (and even then, the synthesized output is identical between the browser and kit paths).

• Tab 1, Compiler. Built on Pyodide (CPython compiled to WebAssembly, v0.29.3); the Module-6 assembler, Module-6a static linker, Module-7/8 VM compiler, and Module-9/10/11 high-level-language frontend all run in-browser. Drives .virtus → .vm → .S → .vof → .hex end-to-end with bit-identical output to the local-Python reference toolchain.
• Tab 2, RV32I-Lite Emulator. Rust source compiled to WebAssembly. Runs the Tab-1-produced .hex at near-native speed; the same fetch / decode / execute cycle Module 5 synthesizes into silicon, observable register-by-register before any FPGA work.
• Tab 3, FPGA Synthesizer. yowasp 0.31 wheel (yosys + nextpnr + gowin_pack as WebAssembly modules); apycula 0.31 ships GW5A-25A.msgpack.xz for the Tang Primer 25K. Full bitstream synthesis in the browser for both Tang Primer 25K (Phase-1 canonical) and Tang Nano 20K (advanced-track alt); bit-identical to the local Sipeed-toolchain output. Flash from your kit when the hardware arrives.

The workbench is the academy's standing rule that recommended tools should run in your browser whenever possible (see the tool integration registry for the full list). Future workbench tabs. A forensic hash validator, a bitstream-trace replay visualizer, a peripheral simulator - follow once the first three tabs are well established in cohort use.

Twelve-Module Topic Flow

The course is organized as twelve modules. Each is backed by a camera-ready chapter prose draft, a supplementary lecture-notes file, and the cross-chapter handouts available in handouts/. The corpus includes 13 chapter drafts + 13 lecture-notes files + 7 cross-chapter handouts. The Static Linker is treated as Module 6a, sitting between the assembler and the virtual machine).

Cross-chapter handouts: cross-chapter-rv32i-lite-encoding-card.md (canonical ISA reference) · cross-chapter-vof-v1-layout-reference.md (Virtus Object Format) · cross-chapter-vm-segment-cheat-sheet.md (VM eight-segment quick reference) · cross-chapter-stdlib-service-reference.md (M11/M12 standard library and OS services) · course prerequisite map · cross-chapter-petzold-reading-guide.md (Petzold-weave catalog with EPUB-verified page numbers) · cross-chapter-sb6141-cousin-mapping-card.md (RE-101 lab-target bridge).

Learning Objectives

From basics to mastery. Each is measurable against a specific module project or against the capstone.

1. Remember. State the eleven-instruction RV32I-Lite ISA and its eight pseudo-instructions; the 32-bit two's-complement integer encoding; the fetch / decode / execute cycle stages; and the names and conventions of the general-purpose register file (x0-x31). (Assessed: closed-book Module-4 quiz; ongoing oral check-ins through Modules 4-8. Reference: handouts/cross-chapter-rv32i-lite-encoding-card.md.)
2. Understand. Explain why a load-store ISA simplifies pipelining, why the linker must resolve symbol references after the assembler emits relocatable objects, and why the virtual machine's stack model decouples high-level-language semantics from any concrete CPU instruction set. (Assessed: Module-6a linker walkthrough; Module-7 stack-machine derivation lecture; Module-8 function-call ABI exercise.)
3. Apply. Implement combinational and sequential logic in an HDL starting from NAND only. Through Boolean primitives, half-adders, full adders, an ALU, registers, and RAM up to RAM16K. Verified in the Virtus HDL simulator against comprehensive test vectors. (Assessed: Modules 1, 2, 3 projects.)
4. Apply. Hand-assemble an RV32I-Lite program from symbolic source, encode the instruction stream into hex, and write a Python two-pass assembler that performs the same translation programmatically; verify with an instruction-by-instruction equivalence check against riscv32-unknown-elf-as. (Assessed: Modules 4 and 6 projects.)
5. Apply. Synthesize a complete CPU from the Modules 1-3 components (instruction memory, ALU, register file, control unit, data memory) using the iverilog → yosys → nextpnr-himbaechel → gowin_pack → openFPGALoader open-source FPGA toolchain (also runnable end-to-end as WebAssembly in the academy workbench Tab 3); flash the bitstream onto a Tang Primer 25K dev board (canonical Phase-1; Tang Nano 20K supported as advanced-track alt); observe a real signal on a probed pin. (Assessed: Module-5 silicon-bring-up project, the "the bytes are now physical" moment.)
6. Apply. Implement a stack-based virtual machine interpreter (Modules 7-8) and a two-pass compiler (Modules 9-11) for a defined high-level language targeting the Module-7 VM, with the standard library and OS services (Modules 11-12) supplying the runtime. (Assessed: Modules 7-12 projects; full-pipeline "Hello World" passing through every layer.)
7. Analyze. Trace a high-level statement through every translation layer, HLL → VM bytecode → assembly → machine code → register transfers, for a non-trivial expression, identifying which translation step performs each transformation. (Assessed: capstone integration walk-through; oral defense Q&A.)
8. Synthesize / Create. Integrate every layer (HDL hardware + assembler + VM + compiler + standard library + OS) into a working application of the student's choice (small game, visualization, text editor, interpreter) running on the Tang Primer 25K FPGA the student personally synthesized (canonical Phase-1; Tang Nano 20K supported as advanced-track alt; workbench-emulator path supported for browser-only-path students until kit hardware arrives or in lieu thereof). (Assessed: capstone. See Capstone section below for the two-part rubric.)

Lab Manifest

Twelve module projects + a static-linker mini-project + the integration capstone. Each project produces a versioned artifact committed to the student's course Git repository, with a lab-notebook entry capturing failure modes encountered, design decisions, and links to the chapter prose and lecture notes the student leaned on.

Bridge to Downstream Courses

CSA-101 is the structural anchor course of the Virtus Academy pipeline. Every downstream course assumes graduates can read assembly fluently (any ISA, the methodology transfers), reason about an unfamiliar processor as a finite collection of design choices rather than as a mystery, and intervene at any layer between transistor and high-level statement.

• → VCA-RE-101 (Reverse Engineering of Embedded Systems). RE-101's binary-analysis lab assumes the student already understands instruction encoding at the bit level. CSA-101 graduates have personally written and debugged the encoder. The SB6141 BE-32 ARM thread woven through Ch 4 + Ch 5 + Ch 6a is an explicit forward-pointer to RE-101's lab target; see handouts/cross-chapter-sb6141-cousin-mapping-card.md for the full silicon / ISA / storage / OS / coprocessor / firmware cousin map.
• → VCA-ADV-101 (Adversarial Techniques). Trust-boundary thinking depends on understanding the layers CSA-101 built. Students who built the compiler can reason about why a compiler-generated artifact shapes the attack surface; students who built the OS can reason about which OS-service calls cross which trust boundaries.
• → VCA-RE-201 (RE of Burst Radio Signals). Same instruction-set-as-design-choice methodology, applied to the protocol-and-encoding layer of RF signals.
• → VCA-CSA-201 (future). Full RV32I + MMU + PMP + driver track + DE10-Nano. CSA-101's RV32I-Lite + Tang Primer 25K + Virtus OS positions students to step into the larger machine without re-establishing fundamentals.
• → VCA-CON-101 (future, Virtus Console capstone build). The Virtus Co-Processor (VCP) introduced as a scale model in CSA-101 chapters becomes a serious peripheral IP pack in the Console course; the Tang Primer 25K workflow returns alongside DE10-Nano + MiSTer with framebuffer + HDMI + audio + GPIO + DualShock 2 decoder peripherals. (The DS2 controllers in the kit have analog sticks and analog button pressure on top of the standard 12-button gamepad interface; the curriculum uses the standard 12-button mapping by default, with the richer analog state exposed in forward-stretch labs.)
• Universal foundation. Beyond named courses, CSA-101 graduates are calibrated for any subsequent computer-systems work: undergraduate operating-systems courses (their CSA-101 OS is the precursor), undergraduate compilers (they built one), graduate computer architecture (they built a small one), embedded firmware engineering, hardware-security research, or graduate-level reverse engineering.

Tool Journal: CSA-101 Originating Entries

The Tool Journal is a per-student Markdown file maintained in the course Git repository, with one paragraph per practitioner tool the first time it is met. CSA-101 originates approximately twenty-three entries (the largest single-course contribution to the diary) spanning HDL simulation, the FPGA toolchain, the software cross-toolchain, debugger, emulator, and the binary-inspection tools that recur across every downstream course.

• Virtus HDL simulator (Module 1). First hardware-simulation tool the student meets; the verification environment for Modules 1-3.
• iverilog (Module 5). Open-source Verilog simulator; verification environment for synthesizable HDL.
• yosys (Module 5). Open-source synthesizer; Verilog → netlist transformation.
• nextpnr-himbaechel (Module 5). Open-source place-and-route for the Gowin GW5A FPGA fabric on the Tang Primer 25K (and GW2A on the Tang Nano 20K advanced-track alt). Also runs as WebAssembly via yowasp inside the academy workbench Tab 3.
• gowin_pack (Module 5). Bitstream packer for Gowin parts.
• openFPGALoader (Module 5). Bitstream-flashing utility; the moment the student loads bytes onto silicon.
• GAO (Gowin Analyzer Oscilloscope) (Module 5). Internal-signal logic analyzer; the FPGA equivalent of the bench-scope from HW-101.
• gtkwave (Module 1+). Waveform visualization; post-mortem inspector for HDL test runs.
• xxd / hexdump (Module 4). Promoted from FND-101 to mandatory daily tool. Bit-level instruction inspection.
• riscv32-unknown-elf-as (Module 6). Reference cross-validation against the Virtus assembler; the path to "is my output really correct?"
• objdump (Module 6). Binary inspection and disassembly verification.
• nm (Module 6). Symbol-table inspection of relocatable objects.
• strings (Module 6). Printable-string extraction; introduced here, used relentlessly in RE-101.
• GNU ld (Module 6a), the reference linker; the Virtus linker the student writes is its pedagogical scale model.
• VOF inspector (Module 6a), Virtus Object Format inspection utility for the locally-defined intermediate format.
• Python 3 (advanced) (Modules 6, 7, 8, 9, 10, 11). Promoted from FND-102; building real toolchain components: assembler, linker, VM, compiler.
• GNU make (Module 5+). Build automation tying HDL synthesis, software toolchain, and tests into a reproducible pipeline.
• gdb (RISC-V cross) (Module 5+). Single-stepping a CPU the student designed.
• qemu-system-riscv32 (Module 5+), RV32 emulation for software tests inconvenient to run on the Tang silicon. The academy workbench Tab 2 supplies a complementary in-browser RV32I-Lite emulator (Rust→Wasm) for quick instruction-level traces.
• Verilator (Module 5, optional). Fast simulation of synthesizable Verilog by C++ translation, for tests too slow under iverilog.
• Compiler Explorer (godbolt.org) (Modules 9-11), the lab in your browser; observe how production compilers transform HLL into assembly for any target ISA.
• git (advanced workflow) (continuous). Promoted from FND-101 introduction to multi-branch, multi-merge, multi-tag working discipline that survives into every later course.
• Lab-notebook discipline (continuous), per-module reflective entries, failure-mode catalog, design-decision rationale; the meta-tool every other course assumes.

Approximately twenty-three originating entries. Combined with HW-101's seven and what RE-101 adds later, the Tool Journal by graduation is a substantive personal reference document the student opens decades later in the middle of a real engagement.

Prerequisite Map

What CSA-101 depends on, and what depends on CSA-101, at cohort-level course-to-course granularity.

Hard prerequisites:

• VCA-FND-101. Binary, hex, Boolean logic, Linux, Git substrate. CSA-101's Modules 1-3 assume FND-101's truth-table / logic-simulator / hex-dump fluency is intact.
• VCA-FND-102, Python 3 fluency. The Virtus toolchain components (assembler, linker, VM, compiler) are written in Python; FND-102 graduates land Modules 6-11 with the language already neutral.

Strongly recommended:

• VCA-HW-101. Bench-instrumentation context for the Module-5 silicon-bring-up. Students arriving without HW-101 are referred to a Module-5 catch-up bench-qualification lab, since the moment of probing a Tang Nano pin and reading a real signal lands harder when the student already knows a multimeter.

Feeds into:

• VCA-RE-101 (central prerequisite for serious binary analysis at professional level).
• VCA-ADV-101 (trust-boundary reasoning; exploit primitives operate at the layers CSA-101 built).
• VCA-RE-201 (instruction-set-as-design-choice methodology applied to RF protocols).
• Future: VCA-CSA-201 (full RV32I + MMU + PMP + driver track + DE10-Nano).
• Future: VCA-CON-101 (Virtus Console capstone build, Tang Nano methodology returns at DE10-Nano scale).

See the course prerequisite map for the academy-wide map including all twelve currently-shipped courses and the named track sequences.

Capstone: Working Computer Running a Real Application

The capstone is the integration of every layer the course built, HDL hardware, assembler, static linker, VM, compiler, standard library, OS. Running a non-trivial application of the student's choice on the Tang Primer 25K FPGA the student personally designed and synthesized (canonical Phase-1 silicon; Tang Nano 20K supported as advanced-track alt). The capstone is graded against integration, not against ambition: a small, complete, working application that exercises every translation layer outscores a half-finished feature-rich one. Students are encouraged to pick something they would genuinely enjoy building - a small game (Tetris, Snake, Pong), a visualization (animated patterns, a low-resolution Mandelbrot sampler), a small interpreter (RPN calculator, BASIC subset), an editor (line-buffer editor with cursor movement), or whatever else genuinely interests them.

Required artifacts

• The synthesized FPGA bitstream and the student's HDL source, committed to the course Git repository.
• The full pipeline source (HLL + compiled VM bytecode + assembly + machine code) with the standard library and OS exercised, all reproducible from a single make invocation.
• A 10-page written technical report at publication catalog: design intent, layer-by-layer description of which course-built component does what, one bug encountered during integration and how it was diagnosed, and a reproducibility section.
• A 5-minute recorded video demo showing the application running on the physical Tang Nano 20K + screen, with brief on-screen narration of which layer is doing what.

Two-tier grading rubric

First, your project must work. The application runs on the Tang Primer 25K bitstream the student synthesized (or Tang Nano 20K bitstream for advanced-track-alt students); the application exercises every translation layer (HDL + assembler + VM + compiler + stdlib + OS); the codebase is in the course Git repository with a working build script; the written report is delivered; the demo is recorded. A failure at Tier 1 triggers a remediation plan. No advanced scoring is applied to an incomplete foundational artifact.

Then we score the report.

• Integration depth (40%). Does the application genuinely exercise every layer? Did the student write HLL code that exercised the compiler's branching constructs, function calls, recursion, and OS-service calls, or does the application reduce to arithmetic-only? Is the FPGA exercising more than a single instruction repeatedly?
• Engineering discipline (30%). Is the build reproducible from a single make? Are the layer interfaces documented? Does the report describe one bug encountered during integration with honest specifics (the failure mode, the diagnostic process, the root cause) not glossed over?
• Demo + report quality (30%). Does the recorded demo show the application on the physical FPGA (not in simulation)? Is it within the 5-minute target? Does the written report read as publication-quality technical prose: figures captioned, every claim grounded in a layer of the codebase, no marketing tone?

A minimum overall grade of B− on Tier 2 is required to earn the VCA-CSA-101 Certificate of Completion. There is no curve. The certificate signals that the holder has personally built a working computer top to bottom and has the integrated mental model to operate at any layer of a computing system, not a participation credential.

Required Hardware & Software

• No additional hardware beyond the standard student compute environment. Everything is HDL-simulated.
• Virtus-original HDL simulator, assembler, VM interpreter, compiler test harness (shipped with the course).
• Python 3 for the assembler and compiler implementations.
• Textbook: Nisan & Schocken, The Elements of Computing Systems, 2nd ed. (MIT Press, 2021). Students purchase individually.

Certification Alignment

University articulation No direct industry cert

No direct industry certification covers CSA-101's content at this depth. The capstone artifact. A working computer the student personally built top to bottom - is a stronger portfolio piece than any multiple-choice exam in this domain. CompTIA, ISC², SANS, and Offensive Security curricula assume rather than teach the layered mental model CSA-101 builds; their courses land harder for graduates who have already built the layers.

University articulation value. CSA-101 covers, at greater depth and with hands-on silicon, the substantive content of any introductory undergraduate computer-architecture course (Patterson & Hennessy textbooks; equivalent ECE / CS curricula). Graduates pursuing university credit can present the capstone artifact + the personal Git repository of twelve module projects + the technical report and demo as articulation evidence; many programs will award credit-by-portfolio at department discretion.

Downstream-course readiness. CSA-101 strengthens preparation for every later Virtus course that touches instruction-set architecture: RE-101 (binary analysis), ADV-101 (trust-boundary reasoning), RE-201 (RF-protocol decoding), future CSA-201 (full RV32I + MMU + PMP), and future CON-101 (Virtus Console capstone build).

Pedagogical-vs-vocational stance. The certificate, the committed Git repository of twelve module projects, and the capstone bitstream + report + demo are the academy's primary credentials. Certs are never required to complete a Virtus Academy course. CSA-101's signal is that the holder has personally built every layer of a computing stack from NAND to a running application. A credential no multiple-choice exam attempts to measure.

Format Prescriptions

Hour budget: ~26 lec hr + ~45 lab hr + ~85 indep hr (= ~155 hr total). The flagship CSA-101 carries the heaviest indep load in the catalog because Modules 6-12 (toolchain + VM + compiler + OS) are individually substantial Python+Verilog builds.

Live (standard cadence)

2 sessions/wk × 90 min each (45 min lecture + 45 min hands-on per session) + 30 min stay-after office time. 14 weeks total (12 modules + integration capstone). Best for college-elective + adult-learning + homeschool-co-op cadence with shared FPGA bench access.

Night class (working-adult cadence)

1-2 sessions/wk in evenings; spread over ~28 weeks. Best for community-college + vocational-tech students with day jobs. The Module-5 silicon-bring-up + Module-12 capstone weeks may need extended-evening blocks (~3 hr) for FPGA flash + bitstream debug; browser-only-path students stay in the workbench until kit hardware lands.

Bootcamp

8 hr/day × 5 days/wk = 40 hr/wk; total ~4 weeks. CSA-101's 155 hr is dense; bootcamp format is feasible but compressed. Expect 8-9 hr days for 4 weeks of focused FPGA + Python toolchain work. Best for adults / age-irrelevant students with prereq comfort + dedicated build time + access to a Tang Primer 25K kit (or browser-only path via the academy workbench).

Async self-paced

Lecture hours via recorded video; lab hours via per-student Tang Primer 25K kit purchase (~$75 starter kit; ~$144 full kit for the Ch 11-12 standard-library labs and the Ch 1-2 discrete-logic build-up; or the browser-only path via the academy workbench); indep hours = student pace. Includes Discord-group access (1-2 days/wk instructor-advertised availability). AI-assistant tier add-on. Live 1:1 tutoring premium tier add-on for FPGA bring-up + Verilog debugging.

High school / homeschool co-op

Adapted live cadence over a school year (~18 weeks at typical school cadence) OR semester (14 weeks at college cadence). Detailed per-syllabus planning available on request. Recommended pairing with HW-101 for bench-instrumentation prereq.

Interested in VCA-CSA-101?

Email interested@virtuscyberacademy.org with your background and interest.

Email interested@virtuscyberacademy.org