Browser Workbench

Drop gate primitives (NAND, AND, OR, NOT, XOR, BUFFER, CLOCK, DFF) onto a canvas, wire them, energize, and watch signals propagate. Includes a logic-analyzer view with per-channel traces, zoom, and mute / solo for sequential-circuit debugging.

12 gate primitives + testbench rows + propagation solver + folded-in logic analyzer (§11.4a) + walkthrough overlay for first-time visitors.

Scroll the 6502 die from top-down overview through per-block reveal. Each week's lab lights up the block it touches: Week 2 gates inside Timing, Week 3 adder in the ALU, Week 4 registers in the file, Week 7 Arlet's core lights every block, Week 8 the bus pulses.

8 scrollytelling scenes; academy-original SVG floorplan; composes with the NAND-budget tracker for a side-panel readout.

Tick each week as your lab adds gates. Bar climbs from 0 toward the 3,500 NAND-equivalents the 6502 needs. Answers the Week-1 question every student asks: am I actually building a CPU?

Per-week checklist + running counter + LocalStorage autosave + compact #badge embed mode + postMessage bridge to other workbench surfaces.

2D board render with bitstream-load animation, 8 GPIO LEDs, 8 input buttons, USB-UART jack. Pick a demo bitstream, click Load, click Run, watch the LEDs count in binary. Same visual the physical board shows after openFPGALoader flashes the same bitstream.

5 pre-assembled demo bitstreams (blink / hello / echo / ramp / halt). Memory-mapped IO at $D012 UART, $D013 LEDs, $D014 buttons matching the real-board pin map.

4-pane workbench: source editor, compiled asm view, register + zero-page inspector, UART console. Hand-write 6502, watch the bytes appear, step through it on an in-browser CPU, see the output land. Easy-6502-tutorial-subset emulator with label resolution.

~50 mnemonics dispatched off the Z5.1 encoder byte-index; 2-pass label resolver; 5 ready-to-load examples; UART at $D012; documented integration seam for the Py6502v compiler.

Drop the 5 Lab 1.1 flashlight components into the 5 slots, energize, watch the LED light up. Probe the circuit with the 2-probe multimeter (voltage + resistance modes) and read the node voltages a real $15 meter would show.

Click-to-select-then-click-to-place; per-slot target-match validation; toggle the switch to demonstrate the open / closed teaching pattern; node-voltage solver hardcoded for the canonical 5-slot topology.

Sketch the circuit, annotate the diagram, caption the session, export as JSON or PNG for instructor review. Engineering-paper background; pencil + eraser + text tools; 4 ink colors; multi-entry sidebar with per-week chapter filter.

Vector strokes (re-importable across devices); LocalStorage autosave with 350 ms debounce; postMessage embed API. Use it from Week 1 onward.

Three-tab toolchain. Compile VirtusLang to .hex through the assembler, VM translator, and static linker for the RV32I-Lite instruction set. Run the resulting .hex on a Rust-to-WASM emulator. Synthesize Verilog through yowasp Yosys + nextpnr to a real Tang bitstream.

Same byte-identical output as the local Sipeed toolchain. Programming the board still happens via the local loader; flash the downloaded .bit file.

Write Py6502v on the left; the same source runs unchanged on host CPython and on an emulated 6502 side-by-side. The dual-execution match indicator IS the pedagogy: byte-identical output on both sides means the contract holds. If your code ever diverges, the first-difference offset tells you where to look.

Real Pyodide hosting the real Py6502v Round 5 compiler + the real py65 emulator in your browser. No JS port, no translation layer. 5 dual-execution goldens (fib / loop / bitwise / call_chain / multi_arg) all match.

Walk through how NES and Game Boy tile bytes split into two interleaved bitplanes that combine into a four-color pixel grid. Hover any byte to highlight its matching pixel. The visual companion to SPK-101's graph-paper tile-decoding lab.

Forward-referenced into RE-101 wk-2 (bit-field decoding for ELF header bytes).

Offline packet-capture analysis in the browser. Reads .pcap and .pcapng; decodes Ethernet through TCP/UDP with L7 protocol shorthand. Wireshark-style display filters (tcp, dns, tls, ip.src, udp.port == 53); click any row to drill into the protocol tree.

Three load paths: curated library (36 academy + Wireshark-wiki samples, click-to-load); your own upload (drag a .pcap onto the page; parsed client-side); ad-hoc URL fetch (direct cross-origin attempt with proxy fallback). Three guided tutorials (pcap basics, TCP 3-way handshake, DNS request-response) walk a new student through the moves.

Drag movable blocks onto a canvas, wire them, press Run. A real Web-Audio flow graph executes in your browser. Eight DSP blocks: Signal Source, Throttle, Filter, FFT Spectrum, Waveform, Constellation, Audio Sink, File Source, File Sink. Live param edits while the graph runs.

v1 MVP per spec-research memo 2026-05-29. Pedagogical reimplementation of GNU-Radio-Companion drag-block / wire / run / visualize. Future block rosters: NET packet pipelines, AI agent pipelines, compiler pipelines.

Interactive finite-state-machine visualizer. Build a hypothesis FSM, then compare it side-by-side with ground truth across JTAG, DNS, and HTTP substrates. First contact with modeling a protocol or interface as a state machine.

State authoring, transition editing, side-by-side compare across the three shipped substrates. Save / load of FSMs is in flight.

Retro programming environment for the 6502, Z80, and NES targets. A full in-browser IDE with editor, assembler, and emulator. Built by Steven Hugg; the academy mirrors it for offline-friendly use in labs and for hand-assembly verification.

Behaves as the upstream project does. Academy hosts a static mirror; upstream updates land on the academy mirror manually rather than on a continuous pull.