VCA-CSA-110: Computer Systems Architecture (RV32I-Lite)
CSA-101 closed at the system line: a 6502 CPU on a Tang Primer 25K, with a toolchain the student wrote from scratch and an OS the student built service-by-service. CSA-110 runs the same arc again on a 32-bit RISC architecture. The chip is now RV32I-Lite, a carefully bounded subset of the RISC-V specification: four instruction formats, fixed 32-bit instruction width, eight registers, and a clean separation between computation and memory that the 6502's 13 addressing modes deliberately collapsed. Every week is the same concept the student already knows from the 6502, now felt at 32-bit width. Architecture Comparison Sidebars make the comparison explicit: you built both; here is where they diverge and why. The capstone is identical to CSA-101's: a working Virtus Console on the same Tang Primer 25K silicon, reached in 14 weeks using the 6502 background as a running start.
workbench for students without hardware. (see hardware platform)Course Overview
CSA-110 is the 32-bit RISC arc of the academy's computer systems sequence. Its audience is CSA-101 + CSA-102 graduates: students who have personally built a 6502 on a Tang Primer 25K and a compiler toolchain that targets it. The pedagogical contract is that CSA-110 is comparative anatomy: every concept is introduced as "here is how the 6502 did it; here is why RV32I-Lite does it differently."
Why build both? The 6502 is historically grounded, small, and irregular:
13 addressing modes, 3 accumulator-class registers, 8-bit data path, 16-bit address space.
RV32I-Lite is clean, regular, and modern: 4 instruction formats, 32-bit data path, 8
registers, 32-bit address space. A student who has built both understands why RISC won the
architectural debate of the 1980s and 1990s, not as an assertion but as a felt engineering
difference. The fixed 32-bit instruction width simplifies the decoder. The three-register
format (rd, rs1, rs2) reduces spill-to-memory. The four-format encoding reduces
the number of encoding edge cases the assembler must handle.
What changes vs CSA-101. The 14-week arc is structurally identical to CSA-101's. The first time through you were learning HDL, FPGA synthesis, and the concept of an instruction set. The second time you already know the tools; the course can move faster through Weeks 1-5 and spend the saved time on the richer toolchain Weeks 8-13. Students typically finish Weeks 1-7 (CPU + assembler + linker) 15-20% faster than they did the 6502 equivalent in CSA-101.
Pedagogy. Three teaching habits from CSA-101 continue throughout CSA-110. Petzold weaves: Petzold's CODE: The Hidden Language of Computer Hardware and Software (1st ed., 1999) is the narrative anchor; ~12 weaves across 14 weeks, each connecting a chapter to the specific design decision the student just implemented. Now the 6502 comparison is live, not historical: "Chapter 17 describes the clock-cycle abstraction; your 6502 CPU used multi-cycle state; your RV32I-Lite CPU uses single-cycle fetch-decode-execute; here is what you gave up and what you gained." Toolchain Diary: ~30 practitioner-tool entries per week, ~10 of which are CSA-102 tools revisited for RV32I-Lite. Architecture Comparison Sidebars: every week file contains a direct 6502 vs RV32I-Lite comparison, with the 6502 experience the student personally has as the baseline.
Curriculum Outline
Fourteen weeks. Weeks 1-7 complete in v0.1; Weeks 8-14 in v0.2.
| Week | Topic | Architecture Comparison Sidebar | Lab focus |
|---|---|---|---|
| 1 | Boolean Logic in Verilog | 6502 ~3,500 NAND-equivalent gates vs RV32I-Lite ~1,400; same physics, different encoding width | NAND-only primitives: AND, OR, NOT, half adder |
| 2 | Boolean Arithmetic: 32-bit ALU | 6502 BCD mode (ADC/SBC + Decimal flag) vs RV32I-Lite (no BCD; pure binary arithmetic) | Full adder, 32-bit ripple adder, ALU (6 ops), IEEE-754 hand encoding |
| 3 | Memory: Registers and RAM | 6502: 3 registers (A, X, Y) + zero page; RV32I-Lite: 8 registers (x0 hardwired zero); CSA-201 expands to 32 | D flip-flop, 8-register file, byte-addressable RAM, metastability drill |
| 4 | Machine Language: RV32I-Lite ISA | 6502: variable-length 1-3 bytes, 13 addressing modes; RV32I-Lite: fixed 32-bit, 4 formats; B-type split immediate | Hand-encode 10 instructions, hand-decode 10 words, sum-to-N, assembler round-trip, Ghidra |
| 5 | CPU Integration and First Boot | 6502 multi-cycle state machine (CSA-101 Arlet core) vs RV32I-Lite single-cycle; pipeline deferred to CSA-201 | Decoder, immgen, cpu.v simulation (sum-to-N = 55), UART boot, seeded failure drill |
| 6 | Assembler: Two-Pass Tokenizer | 6502 flat-address one-pass; RV32I-Lite B-type forward references force two-pass; VOF v1 vs flat 6502 binary | pass1.py, encode.py (11 instructions + 8 pseudo-ops), pass2.py, VOF emitter, round-trip |
| 7 | Static Linker | Static linking vs Py6502v flat model; symbol table as the data structure flat 6502 could skip | Symbol resolution, relocation patching, link two files, boot on silicon |
| 8 | VM I: Stack Arithmetic | Stack VM vs 6502 register-direct codegen; RV32I-Lite 8-register file vs 6502's 256-byte hardware stack | Stack-arithmetic translator + memory segments + end-to-end simulation |
| 9 | VM II: Function Calls | RV32I-Lite JALR (1 cycle) vs 6502 JSR+stack-pull (6 cycles); calling convention comparison | Program-flow translator + function-call protocol + recursive factorial on silicon |
| 10 | Compiler I: Syntax Analysis | CSA-102 Py6502v tokenizer vs VirtusLang tokenizer: same structure, different grammar and code-gen target | Tokenizer + recursive-descent parser + parse-tree round-trip |
| 11 | Compiler II: Code Generation | Tree-walk codegen vs SSA-IR (LLVM); CSA-102 flat codegen vs three-register RV32I-Lite codegen | Symbol table + codegen + end-to-end on silicon + Ghidra on own compiler output |
| 12 | Compiler III: OS-Aware Compilation | Py6502v flat runtime vs Virtus OS stdlib method dispatch; hosted vs freestanding compilation models | Multi-file compilation + Virtus OS library calls + Virtus Console HDMI output |
| 13 | Virtus OS | Virtus OS vs POSIX vs 6502 minimal runtime from CSA-102; CSA-201 OS-hardening forward promises | Math + Memory/String/Array + Screen + Keyboard + VCP integration + compliance suite |
| 14 | Capstone Delivery | Closing bridge: where RV32I-Lite leads next (CSA-201, CON-101, RE-101) | Full Virtus Console integration + demo video + write-up with CSA-101 comparison |
Learning Outcomes
- Remember. Recite the RV32I-Lite instruction set (11 instructions plus 8 pseudo-instructions, 4 formats, 8 registers). Name the seven stages of the toolchain from source to silicon.
- Understand. Explain the differences between the 6502 and RV32I-Lite architectures at the encoding, register, and memory-access levels, using the implementations you personally built as evidence.
- Apply (hardware). Implement the full RV32I-Lite data path in Verilog: 32-bit ALU, 8-register file, instruction decoder, fetch-decode-execute cycle. Synthesize to a Tang Primer 25K bitstream. Flash and run.
- Apply (toolchain). Write a two-pass assembler, a static linker, a VM translator, a compiler front end, and a compiler back end, all targeting RV32I-Lite. Build Virtus OS. Chain them end-to-end.
- Analyze. Trace one source-code line through every stage of your toolchain. Do the same trace for the CSA-102 6502 toolchain and identify exactly where the two paths diverge and why.
- Create. Deliver a working Virtus Console: your RV32I-Lite CPU on Tang Primer 25K silicon; your Virtus OS; a program using standard-library services; a demo video; a write-up comparing the CSA-101 and CSA-110 build experiences.
Hands-On Labs
One lab per week. Each lab names a specific deliverable and a verification command.
- Lab 1: NAND-only Verilog primitives. AND, OR, NOT, half adder from NAND gate instances only.
- Lab 2: 32-bit ALU. Full adder, 32-bit ripple chain, subtraction via two's complement, SLT (signed). IEEE-754 hand encoding of three values.
- Lab 3: Register file. 8 registers; x0 hardwired zero; simultaneous read-write semantics; metastability drill.
- Lab 4: RV32I-Lite ISA. Hand-encode 10 instructions with bit-field breakdown. Hand-decode 10 hex words. Sum-to-N assembly program. Assembler round-trip (
riscv64-linux-gnu-as). Ghidra first RISC-V encounter. - Lab 5: CPU integration. Instruction decoder for all 11 instruction types. Single-cycle CPU simulation: sum-to-N = 55. Synthesis report. UART output on silicon. Seeded failure drill.
- Lab 6: Two-pass assembler. Pass 1 tokenizer, label collector. Encoder for all 11 instructions + 8 pseudo-instructions. Pass 2 + VOF v1 emitter. Round-trip verification against
riscv64-linux-gnu-as. - Lab 7: Static linker. Multi-file symbol resolution. Relocation patching. Link sum-to-N + math stub. Boot on silicon. Seeded undefined-symbol error. Toolchain Diary forward promise to CSA-201 register allocator.
- Lab 8: Stack-arithmetic VM translator. Push/pop, arithmetic ops, memory segments. End-to-end simulation.
- Lab 9: Function-call VM translator. Program-flow ops. Recursive factorial on Tang Primer 25K.
- Lab 10: Compiler front end. Tokenizer. Recursive-descent parser. Parse-tree round-trip.
- Lab 11: Compiler code generation. Symbol table with class/subroutine scope. End-to-end on silicon. Ghidra on own compiler output. Five-category codegen baseline measurement.
- Lab 12: OS-aware compiler. Multi-file compilation. Virtus OS library calls. Virtus Console HDMI output.
- Lab 13: Virtus OS. All required services. Compliance suite. VCP integration.
- Lab 14 / Capstone: Full Virtus Console. Bitstream + toolchain + program + demo video + write-up.
The CSA-110 Capstone
The capstone is a working Virtus Console on Tang Primer 25K silicon. Same destination as CSA-101. The grader verifies three dimensions equally: the console works (bitstream flashes, program boots, demo video shows real output); the toolchain reproduces (a grader can rebuild the binary byte-for-byte from the student's source); and the write-up is honest (five sections reflecting actual work, with Section 4 naming a moment where the RV32I-Lite experience genuinely surprised the student versus the 6502 experience).
No minimum complexity threshold. A simple program that boots reliably and is honestly written up earns the same grade as an elaborate program that crashes on cold boot. The distinctive deliverable for CSA-110 graduates — the thing no CSA-101-only student can write — is the comparative reflection: what the 6502 build felt like versus what the RV32I-Lite build felt like, and what that felt difference reveals about architectural philosophy.
What students arrive knowing
| From CSA-101 | From CSA-102 | New in CSA-110 |
|---|---|---|
| HDL workflow (Verilog) | Assembler design | RV32I-Lite instruction encoding |
| FPGA synthesis (Gowin/Apicula) | Py6502v compiler toolchain | Two-pass assembly (forward references) |
| Simulation (iverilog + GTKWave) | Flat-address linker model | VOF v1 object file format + static linker |
| Tang Primer 25K bring-up | 6502 calling convention | RV32I-Lite calling convention (JALR vs JSR) |
| Virtus Console architecture | VM translator concept | Fixed 32-bit encoding + 3-register format codegen |
What CSA-110 deliberately omits
CSA-110 covers RV32I-Lite: 11 base instructions, 8 pseudo-instructions, 8 registers, no pipelining, no hardware multiplier, no privileged ISA, no virtual memory. These are named omissions with forward pointers, not gaps.
| Omitted feature | CSA-201 module that recovers it |
|---|---|
| Full 32 registers (CSA-110 uses 8) | Module 1: Full RV32I calling convention |
| Hardware multiply / divide | Module 1: M extension (mul, div, rem; ~1,000× speedup over software multiply) |
Privileged ISA / ecall | Module 2: U/S-mode split; syscall trap mechanism |
| Pipelining | Module 1 lab: 5-stage pipeline on CSA-110 CPU core |
| Virtual memory (MMU) | Module 7: Sv32 paged virtual memory |
| Compiler register allocator | Module 3: register allocator pass; closes Lab 7.4 forward promise |
| W^X memory protection | Module 8: PMP + W^X enforcement |
Position in the curriculum
CSA-110 sits at Belt 4, between the 6502 pair (CSA-101 + CSA-102) and the advanced course (CSA-201). Students who complete CSA-110 hold the same end-state as CSA-101 graduates but with a second architecture under their belt and a fluency in architectural comparison that neither course alone produces.
| Course | Architecture | What it provides |
|---|---|---|
| CSA-101 | 6502 (8-bit, CISC-adjacent) | First stack build; HDL + toolchain fluency; Tang Primer 25K bring-up |
| CSA-102 | 6502 toolchain (Py6502v) | Assembler, compiler, NES-cart capstone; toolchain depth |
| CSA-110 (this course) | RV32I-Lite (32-bit RISC) | Second stack build; RISC vs CISC felt difference; CSA-201 gateway |
| CSA-201 | Full RV32I + M + privileged ISA | Recovers every deliberate omission from CSA-110 |
CSA-110 also unlocks CON-101 (Virtus Console game development) and RE-101 (reverse engineering the SB6141 cable modem). The RV32I-Lite encoding fluency from Week 4 and the silicon instinct from Week 5 are prerequisites both courses use immediately.
Classroom
Full course content (14 weekly modules, labs, capstone specification, instructor guide) lives in the Virtus Cyber Academy classroom at portal.virtuscyberacademy.org/csa-110/. Weeks 1-7 are available now. Weeks 8-14 follow in v0.2.
Register interest
CSA-110 is not yet open for enrollment. The first cohort will run once CSA-101 and CSA-102 have produced graduates. If you are working through the CSA track and want to be notified when CSA-110 cohorts open, email interested@virtuscyberacademy.org with subject line "VCA-CSA-110 interest."
No obligation. We will notify you when the first cohort is scheduled.